DDR5 Interface Analysis with HyperLynx

This video explains how HyperLynx can help you design and verify electronic systems that use DDR5 memory. Learn about the challenges of simulating DDR5 and the advanced techniques HyperLynx uses to do so, including utilizing IBIS-AMI models and protocol-specific, JEDEC-based analysis. You’ll see that Hyperlynx provides a comprehensive, integrated flow that covers both design (pre-route simulation) and verification (post-route simulation). HyperLynx signal integrity analysis produces complete, detailed reports that tell you which signals passed, which signals failed, and by how much, in addition to lots of supporting detail. Both pre-route and post-route simulations use the same analysis process and produce the same reports, making it easy to compare your pre-route expectations to actual post-route results. See how HyperLynx supports DDR5 interface analysis by utilizing the latest DDR5 AMI model features. ▶️ Chapters: 0:11 New technologies mean new simulation models and techniques 2:00 Channel equalization in DDR5 interface 2:23 DDR5 bit error rate requirements 3:42 Using simulation for design vs. Verification 4:59 Post-route verification flow 6:08 HyperLynx DRC 6:39 DDRx Batch Wizard 8:13 Crosstalk analysis 9:38 Protocol-aware, interface-level analysis 10:10 Comprehensive detailed reporting 10:54 Large designs in HyperLynx 11:34 See HyperLynx in action 14:29 DDR5 design & verification with HyperLynx summary ▶️ Connect with us: » LinkedIn: https://sie.ag/3JzTqfB » Blog: https://sie.ag/3lC4Ozl » HyperLynx Community Discussion Board: https://sie.ag/40baPSL » Twitter: https://sie.ag/3JxPQCI #PCBDesign #SignalIntegrity #PowerIntegrity #ElectricalEngineering #Engineering #DDR5